Altera Cyclone V Device Handbook page 687

cv_54011
2013.12.30
Bits
30 Card Error Summary (CES)
29:6 Reserved
5 End of Ring (ER)
4 Second Address Chained (CH)
3 First Descriptor (FS)
2 Last Descriptor (LD)
1 Disable Interrupt on Completion (DIC)
0 Reserved
The DES1 descriptor field contains the buffer size.
Table 11-5: Internal DMA Controller DES1 Descriptor Field
Bits
31:26 Reserved
SD/MMC Controller
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Name
The CES bit indicates whether a transaction error occurred.
The CES bit is the logical OR of the following error bits in
the rintsts register.
• End-bit error (ebe)
• Response timeout (rto)
• Response CRC (rcrc)
• Start-bit error (sbe)
• Data read timeout (drto)
• Data CRC for receive (dcrc)
• Response error (re)
When set to 1, this bit indicates that the descriptor list
reached its final descriptor. The internal DMA controller
returns to the base address of the list, creating a descriptor
ring. ER is meaningful for only a dual-buffer descriptor
structure.
When set to 1, this bit indicates that the second address in
the descriptor is the next descriptor address rather than
the second buffer address. When this bit is set to 1, BS2
(DES1[25:13]) must be all zeros.
When set to 1, this bit indicates that this descriptor contains
the first buffer of the data. If the size of the first buffer is 0,
next descriptor contains the beginning of the data.
When set to 1, this bit indicates that the buffers pointed to
by this descriptor are the last buffers of the data.
When set to 1, this bit prevents the setting of the TI/RI bit
of the internal DMA controller status register (idsts) for
the data that ends in the buffer pointed to by this descriptor.
Name
Internal DMA Controller Descriptor Fields
Description
†
Description
11-9
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