Reverse Serial Pre-Cdr Loopback - Altera Cyclone V Device Handbook

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Reverse Serial Pre-CDR Loopback

Reverse serial loopback is often implemented when using a bit error rate tester (BERT) on the upstream

transmitter.

Figure 6-4: Reverse Serial Loopback Datapath

Transmitter PMA

Reverse Serial

Loopback Datapath

Receiver PMA

Note: Grayed-out blocks are not active when the reverse serial loopback is enabled.

Related Information

Altera Transceiver PHY IP Core User Guide

Reverse Serial Pre-CDR Loopback

This section describes reverse serial pre-CDR loopback debugging with a data path through the

rx_serial_data port to the tx_serial_data port, and before the receiver CDR.

You can enable reverse serial pre-CDR loopback through the reconfiguration controller.

For further details, refer to the Altera Transceiver PHY IP Core User Guide.

In reverse serial pre-CDR loopback, the data received through the rx_serial_data port is looped back

to the tx_serial_data port before the receiver CDR. The received data is also available to the FPGA

logic. No dynamic pin control is available to select or deselect reverse serial pre-CDR loopback.

The transmitter buffer is the only active block in the transmitter channel. You can change the VOD on the

transmitter buffer through the dynamic reconfiguration controller. The pre-emphasis settings for the

transmitter buffer cannot be changed in this configuration.

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Transmitter PCS

Receiver PCS

Transceiver Loopback Support

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