Error Detection Process - Altera Cyclone V Device Handbook

CV-52008
2013.11.12
Table 8-6: Error Type in EMR
The following table lists the possible error types reported in the error type field in the EMR.
Error Type
Bit 3 Bit 2
0 0
0 0
0 0
1 1
Table 8-7: JTAG Fault Injection Register Map
Field Name
Error Byte
Value
Byte Location
Error Type

Error Detection Process

When enabled, the user mode error detection process activates automatically when the FPGA enters user
mode. The process continues to run until the device is reset even when an error is detected in the current
frame.
Figure 8-4: Error Detection Process Flow in User Mode
Timing
The
CRC_ERROR
an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever
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Bit 1 Bit 0
0 0 No CRC error.
0 1 Location of a single-bit error is identified.
1 0 Location of a double-adjacent error is identified.
1 1 Error types other than single-bit and double-adjacent errors.
Bit Range
31:0
41:32
45:42
Bit 45 Bit 44
0 0
0 0
0 0
Calculate and
Receive
Compare
Data Frame
CRC Values
pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When
Description
Contains the location of the bit error that
corresponds to the error injection type to this
field.
Contains the location of the injected error in
the first data frame.
Specifies the following error types.
Bit 43 Bit 42
0 0 No error
0 1 Single-bit error
1 0 Double adjacent error
Error
Detected?
Yes
Update Error
Message Register
(Overwrite)
Error Detection Process
Description
Pull CRC_ERROR
No
Signal Low for
32 Clock Cycles
Drive
Search for
CRC_ERROR
Error Location
Signal High
8-7
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