Sru Sport Receive Master; Sru Sport Signal Integrity - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

SRU Programming
Table 10-3. SPORT DAI/SRU Signal Connections (Cont'd)
Internal Node
SPORT7–0_CLK_PBEN_O
SPORT7–0_FS_PBEN_O
SPORT7–0_DA_PBEN_O
SPORT7–0_DB_PBEN_O
SPORT7–0_TDV_PBEN_O

SRU SPORT Receive Master

If the SPORT is operating as receive master, it must feed its master output
clock back to its input clock. This is required to trigger the SPORT's state
machine. Using SPORT 4 as an example receive master, programs should
route
SPORT4_CLK_O
operating as a transmitter in master mode.

SRU SPORT Signal Integrity

There is some sensitivity to noise on the clock (
sync (
SPORTx_FS
receiver. By correctly programming the signal routing unit (SRU) clock
and frame sync registers, the reflection sensitivity in these signals can be
avoided.
Figure 9-9 on page 9-19
the SRU maps to:
• The signal from the DAI pin (
clock input (
• The SPORT clock output (
(
DAI_PBxx_I
10-6
www.BDTIC.com/ADI
DAI Connection
Group F
to
SPORT4_CLK_I
) signals when the SPORT is configured as a master
shows the default routing of the serial port where
)
SPORTx_CLK_I
SPORTx_CLK_O
)
ADSP-214xx SHARC Processor Hardware Reference
SRU Register
. This is not required if the SPORT is
SPORTx_CLK
) back to the SPORT
DAI_PBxx_O
) to the pin buffer input
) and frame