Debug Features; Dai Shadow Registers; Dpi Shadow Registers; Loop Back Routing - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Debug Features

registers provide a way to specify which interrupts to notice and handle,
and which interrupts to ignore. These dual registers function like
does, but with a higher degree of granularity.

The DAI/DPI interrupt controller has the same interrupt latency
like the core interrupt controller which takes 6 cycle latency to
respond to asynchronous interrupts.
Note that
IRPTL
ters (
DAI_IMASK_x
Debug Features
The following sections describe features that can be used to help in debug-
ging the DAI.

DAI Shadow Registers

The
DAI_IMASK_L_SH
for the
DAI_IMASK_L
registers returns data in
out clearing the contents of these registers.

DPI Shadow Registers

The
DPI_IMASK_SH
read of this register (RO) returns data in
contents of this register.

Loop Back Routing

The serial peripherals (SPORT and SPI) support an internal loop back
mode. If the loop back bit for each peripheral is enabled, it connects the
transmitter with the receiver block internally (does not signal off-chip).
9-40
www.BDTIC.com/ADI
and are system registers. All DAI interrupt regis-
LIRPTL
) are memory mapped registers.
and
DAI_IMASK_H_SH
and
DAI_IMASK_H
DAI_IMASK_L
shadow register is provided for register
ADSP-214xx SHARC Processor Hardware Reference
shadow registers are provided
registers respectively. Reads of these
and respectively with-
DAI_IMASK_H
without clearing the
DPI_IMASK
IMASK
. A
DPI_IMASK