Sport Receive Buffer Registers (Rxspx; Sport Divisor Registers (Divx - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Serial Port Registers

SPORT Receive Buffer Registers (RXSPx)

The 32-bit
RXSPx
operations. The reset value for these registers is undefined. For more
information on how receive buffers work, see
Buffers (TXSPxA/B, RXSPxA/B)" on page
registers are:
RXSPx
RXSP0A – 0xc61
RXSP1A – 0xc65
RXSP2A – 0x461
RXSP3A – 0x465
RXSP4A – 0x861
RXSP5A – 0x865
RXSP6A – 0x4861
RXSP7A – 0x4865

SPORT Divisor Registers (DIVx)

The addresses of the
DIV0 – 0xc02
DIV2 – 0x402
DIV4 – 0x802
DIV6 – 0x4802
These registers, shown in
These registers contain two fields:
• Bits 15–1 are
value for internally-generated
A-44
registers hold the input data from serial port receive
RXSP0B – 0xc63
RXSP1B – 0xc67
RXSP2B – 0x463
RXSP3B – 0x467
RXSP4B – 0x863
RXSP5B – 0x867
RXSP6B – 0x4863
RXSP7B – 0x4867
registers are:
DIVx
DIV1 – 0xc03
DIV3 – 0x403
DIV5 – 0x803
DIV7 – 0x4803
Figure A-20, have an undefined reset value.
. These bits identify the serial clock divisor
CLKDIV
---------------------- - 1
CLKDIV =
8 f
ADSP-21368 SHARC Processor Hardware Reference
"Transmit and Receive Data
5-67. The addresses of the
as follows:
SCLK
f
CCLK
–
( )
SCLK