Single Update Mode; Double Update Mode - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Operation Modes
PWMPERIOD/2
-PWMPERIOD/2
PWM INTERRUPT
LATCH
Figure 7-7. Operation of Internal PWM Timer (Edge Aligned)

Single Update Mode

In single update mode, a single PWM interrupt is produced in each PWM
period. The rising edge of this signal marks the start of a new PWM cycle
and is used to latch new values from the PWM configuration registers
( and
PWMTM PWMDT
two-phase timing unit. In addition, the
the output control unit on the rising edge of the PWM interrupt latch
pulse. In effect, this means that the characteristics and resultant duty
cycles of the PWM signals can be updated only once per PWM period at
the start of each cycle. The result is that PWM patterns that are symmetri-
cal about the mid-point of the switching period are produced.

Double Update Mode

In double update mode, there is an additional PWM interrupt latch pulse
produced at the mid-point of each PWM period. The rising edge of this
new PWM pulse is again used to latch new values of the PWM
7-22
www.BDTIC.com/ADI
PWM TIME DECREMENTS FROM
PWMPERIOD/2 TO -PWMPERIOD/2
) and the PWM duty cycle registers (
ADSP-214xx SHARC Processor Hardware Reference
PWM TIME DECREMENTS FROM
-PWMPERIOD/2 TO PWMPERIOD/2
1
PCLK
PWMCHx
register is also latched into
PWMSEG
) into the