Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 598

SRU Programming
SRU Programming
To use the PCG, route the required inputs using the SRU as described
Table 14-3. Also, use the SRU to connect the outputs to the desired DAI
pin.
Table 14-3. PCG DAI/SRU Connections
Internal Nodes
Inputs
PCG_SYNC_CLKA_I
PCG_SYNC_CLKB_I
PCG_SYNC_CLKC_I
PCG_SYNC_CLKD_I
PCG_EXTA_I
PCG_EXTB_I
PCG_EXTC_I
PCG_EXTD_I
MISCA2_I
MISCA3_I
MISCA4_I
MISCA5_I
Outputs
PCG_CLKA_O
PCG_CLKB_O
PCG_CLKC_O
PCG_CLKD_O
PCG_FSA_O
PCG_FSB_O
PCG_FSC_O
PCG_FSD_O

A PCG clock output cannot be fed to its own input. Setting
SRU_CLK4[4:0] = 28
PCG_CLKA_O
logic low, not to
14-4
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DAI Group
Group A
Group E
Group A, D
Group A, D, E
Group D
Group C, D, E
Group D
connects
. Setting
SRU_CLK4[9:5] = 29
. The clock and frame sync signals of
PCG_CLKB_0
ADSP-214xx SHARC Processor Hardware Reference
DPI Group SRU Register
SRU_CLK4
SRU_CLK5
SRU_EXT_MISCA
Group B
Group B
to logic low, not to
PCG_EXTA_I
connects to
PCG_EXTB_I