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Clocking
• PWM status registers (PWMSTATx). Report the phase and mode
status for each PWM group.
The traditional read-modify-write operation to enable/disable a
peripheral is different for the PWMs.
"Global Control Register (PWMGCTL)" on page A-67.
Clocking
The fundamental timing clock of the PWM controllers is peripheral clock
(
).
PCLK
Functional Description
The individual elements shown in
following sections.
Two-Phase PWM Generator
Each PWM group is able to generate complementary signals on two out-
puts in paired mode or each group can provide independent outputs in
non-paired mode.
Switching Frequencies
The 16-bit read/write PWM period registers,
PWM switching frequency.
The PWM generator does not support external synchronization
mode.
The fundamental timing unit of the PWM controller is
for a 200 MHz peripheral clock, the fundamental time increment is 5 ns.
The value written to the
7-6
www.BDTIC.com/ADI
Figure 7-1
register is effectively the number of
PWMPERIODx
ADSP-214xx SHARC Processor Hardware Reference
For more information, see
are described in detail in the
, control the
PWMPERIOD3–0
. Therefore,
PCLK
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