Chained Dma Interrupts; Transfer Completion Types - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Interrupts

Chained DMA Interrupts

For chained DMA, the channel generates interrupts in one of two ways:
1. If = 1, (bit 19 of the chain pointer register is the program con-
PCI
trolled interrupts, or
the chain.
2. If = 0, an interrupt occurs at the end of a completed chain. For
PCI
more information on DMA chaining, see
on page
Figure 2-4 shows the PCI timing during TCB loading. After the DMA
count for the last word of frame N becomes zero, the PCI interrupt is
latched. At the same time the DMA reloads the TCB for that specific
channel (assuming no higher priority DMA requests). Finally the DMA
channel resumes operation for frame N–1.
FRAME N
DMA
IOD BUS
Count=1
Figure 2-4. DMA Chaining

By clearing a channel's
mask the DMA complete interrupt for a DMA process within a
chained DMA sequence.

Transfer Completion Types

The next two sections describe the two types of interrupts that are used to
signal interrupt completion. These are based on the type of peripheral
used.
2-46
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bit) an interrupt occurs for each DMA in
PCI
2-22.
PCI INTERRUPT
LATCHED FOR
FRAME N
DMA
Count=0
PCI
ADSP-214xx SHARC Processor Hardware Reference
"Functional Description"
DMA Channel DMA
TCB Loading Count=N
bit during chained DMA, programs
FRAME N-1
DMA
Count=N-1