Fetching Isa Instructions From External Memory - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

selected boot mode. However for all boot modes except the reserved boot
mode, the default
Therefore, if instruction fetch from external memory is desired upon reset,
the program needs to set up the appropriate interrupt vector tables in
internal memory as part of the boot-up code before beginning to fetch
these instructions.
When an unmasked interrupt occurs and is serviced, program execution
automatically jumps to the location of the corresponding interrupt vector
table in internal memory. Upon returning from the interrupt, the
sequencer resumes fetching instructions from external memory because
locating the IVT in external memory is not supported.

Fetching ISA Instructions From External Memory

The SDRAM/DDR2 controllers along with the processor core incorpo-
rates appropriate enhancements so that instruction code can be fetched
from the SDRAM/DDR2 at the maximum possible throughput.
Throughput is limited only by the SDRAM/DDR2 when the code is non
sequential.
The address map for code is same as for data. Each address refers to a
32-bit word. Any address produced by the sequencer is checked to
deter-mine if it falls in the external memory and if so, the SDRAM/DDR2
controllers initiate access to the SDRAM/DDR2. Because the sequencer
address bus is limited to 24 bits, only part of the external memory address
area can be used to store code. As explained in the following section, the
address generated by the sequencer undergoes translation to produce a
physical address, since the SDRAM data bus width is less than 48 bits.

Whether fetching ISA or VISA instructions, the IVT needs to be
placed in the ISA normal word space (NW).
ADSP-214xx SHARC Processor Hardware Reference
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bit setting is 1 (
IIVT
).
SYSCTL
External Port
3-89