Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 378

Functional Description
The range of T
AL
and the corresponding duty cycles are:
d
d
The minimum permissible value of T
sponds to a 0% duty cycle, and the maximum value is T
switching period, which corresponds to a 100% duty cycle. Negative val-
ues are not permitted.
The output signals from the timing unit for operation in double update
mode are shown in
switching frequency, dead time, and duty cycle are all changed in the sec-
ond half of the PWM period. The same value for any or all of these
quantities can be used in both halves of the PWM cycle. However, there is
no guarantee that a symmetrical PWM signal will be produced by the tim-
ing unit in this double update mode. Additionally,
the dead time is inserted into the PWM signals in the same way as in sin-
gle update mode.
In general, the on-times (active low) of the PWM signals over the full
PWM period in double update mode can be defined as:
(
T
=
S
PWMPERIOD

1
T -----------------------------------------
= +

L
A
2
7-10
www.BDTIC.com/ADI
is:
[ ×
0 2 PWMPERIOD
–
t
1
-- - PWMCHA PWMDT
AH
------- -
------------------------------------------------------------------- -
= = +
AH
T 2
S
t
1
-- - PWMCHA PWMDT
AL
------ -
------------------------------------------------------------------- -
= = +
AL
T 2
S
Figure 7-3. This illustrates a general case where the
PWMPERIOD
+
1
PWMPERIOD
2
----------------------------------------- PWMCHA
–
2
ADSP-214xx SHARC Processor Hardware Reference
× ]
t
PCLK
–
PWMPERIOD
–
PWMPERIOD
and T is zero, which corre-
AH AL
Figure 7-3
) t ×
PWMPERIOD
2
PWMCHA PWMDT
– –
1 2
, the PWM
S
shows that
PCLK

×
t
PWMDT
–

PCLK
1 2