Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 370

Features
Table 7-1. PWM Specifications (Cont'd)
Feature
DMA Data Access
DMA Channels
DMA Chaining
Boot Capable
Local Memory
Clock Operation
Features
The following is a brief summary of the features of this interface.
• Four independent PWM units
• 2-phase output timing unit
• Center or edge aligned PWM
• Single or double update PWM timer period
• Output logic allows redirection of 2-phase output timing
• PWM units can operate synchronized to each other
• Complementary outputs allows bridge based applications
A block diagram of the module is shown in
the four output PWM signals on pins AH to BL is controlled by four pri-
mary blocks.
• The two-phase PWM timing unit, which is the core of the PWM
controller, generates two pairs of complemented center based
PWM signals.
7-2
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Availability
N/A
N/A
N/A
N/A
No
f
PCLK
ADSP-214xx SHARC Processor Hardware Reference
Figure 7-1. The generation of