Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 924

Peripheral Registers
Table A-59. MLB_SDCR Register Description (RO)
Bit Name
31–0 SDATA
System Mask Configuration Register (MLB_SMCR)
This register, described in
tem status interrupts. When a mask bit is set, the corresponding system
channel interrupt is masked.
31 30
15
SMMU
System Masks MLB Unlock
SMML
System Masks MLB Lock
SMSC
System Masks Subcommand
Figure A-47. MLB_SMCR Register
Table A-60. MLB_SMCR Register Bit Descriptions (RW)
Bit Name
0 SMR
2 SMNU
1 SMNL
3 SMCS
A-98
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Description
System Channel Data.
Table A-60, allows system software to mask sys-
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
System Masks Reset Command. When set, this bit masks system inter-
rupts for Mlb Reset system command.
System Masks Network Unlock. When set, this bit masks system inter-
rupts for the MOST_unlock system command.
System Masks Network Lock. When set, this bit masks system interrupts
for the MOST_Lock system command.
System Masks Channel Scan. When set, this bit masks system interrupts
for MlbScan system command.
ADSP-214xx SHARC Processor Hardware Reference
21 20 19 18 17 16
6 5 4 3 2 1 0
SMR
System Masks Reset Command
SMNU
System Masks Network Unlock
SMNL
System Masks Network Lock
SMCS
System Masks Channel Scan