Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 697

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As a second example, if there is a +50 ppm error in the 1Hz frequency,

this also translates into 86400 × 50ppm seconds (=–4.32 seconds) error at

the end of the day which in this case the time has to be subtracted. This is

corrected in the RTC by counting 00:00:00 to 00:00:03 twice, so that the

time is effectively subtracted. As soon as the RTC reaches 00:00:04, the

error reduces to –0.32 seconds over the course of the previous day and

accumulated error is minimized.

When the RTC is powered up for the first time, the calibration values are

written once to ensure proper functionality. (If they are not to be used,

write 0000). These register bits are sticky, which means that once set, they

retain their value irrespective of the status of core supply.

The addition or subtraction of time can only be in integer multiples of

seconds. Zero to seven seconds can be added or subtracted using 4 bits.

The MSB indicates addition (0) or subtraction (1). The three LSBs indi-

cate number of seconds (0 – 7 represented by their binary 3 bit

equivalents). Because the clock runs at a time period of one second (@ 1

Hz frequency) 0.25 or 0.5 second resolution is not possible.

The calibration technique introduces a guard band for alarm by defini-

tion. In case the alarm is set within the duration of the time

(Day:00:00:00 to Day:00:00:06) corrected by the calibration register,

then it occurs at the nearest corrected time. This is shown in the following

two examples.

jumps from 23:59:59 to 00:00:05 due to calibration. If the alarm is

set to 00:00:01, it occurs at the RTC time 00:00:05.

clock counts from 00:00:00 to 00:00:04 twice and then moves to

00:00:05. If the alarm is set to 00:00:01, it occurs at the RTC time

ADSP-214xx SHARC Processor Hardware Reference

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Real-Time Clock—ADSP-2147x

value in the

value in the

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