Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 496

Operation Modes
for every frame, and therefore emulates I
between multichannel and I
L/RCLK
BCLK
SLOT 1
DATA
LEFT 0
Figure 10-9. Packed Mode 128 Operation
Clocking Options
In packed mode, the serial ports can either accept an external serial clock
or generate it internally. The
selection of these options. For internally-generated serial clocks, the
bits in the
DIV DIVx
programs can select whether the serial clock edge is used for sampling or
driving serial data and/or frame syncs. This selection is performed using
the bit in the
CKRE
Frame Sync Options
The frame sync period in packed mode is defined as:
FS period =
SLEN
The frame sync can be configured in master or slave mode depending on
the bit. Moreover the logic level can be changed with the
IMFS
10-38
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2
S mode.
SLOT 2 SLOT 3 BLANK SLOT
LEFT 1 LEFT 2 4 SCLK
BCLK
MSB MSB
20-BIT DATA MSB
–1 –2
MSB MSB
16-BIT DATA MSB
–1 –2
ICLK
register configure the serial clock rate. Finally,
register.
SPCTL
× number of channels.
ADSP-214xx SHARC Processor Hardware Reference
2
S mode. So it is a hybrid
SLOT 4 SLOT 5
RIGHT 0 RIGHT 1
MSB MSB LSB LSB LSB
–3 –4 +4 +3 +2
MSB MSB
LSB
–3 –4
bit in the register determines the
SPCTL
SLOT 6 BLANK SLOT
RIGHT 2 4 SCLK
LSB
LSB
+1
CLK-
bit.
LMFS