Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 491

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Multichannel mode operates completely independently and each
uses its own
signal synchronizes the channels and restarts each multichannel
FS
sequence. The
data word. The
period =
FS
configured in master or slave mode based on the setting of the
bit and the logic level can be changed using the
can be changed if bit 2 (
Frame Sync Delay (MFD)
The 4-bit field (bits 4–1) in the multichannel control registers
MFD
( ) specifies a delay between the frame sync pulse and the first data
SPMCTLx
bit in multichannel mode. The value of
cycles of the delay. Multichannel frame delay allows the processor to work
with different types of telephony interface devices.
A value of zero for
first data bit. The maximum value allowed for
may occur before data from the last frame has been received, because
blocks of data occur back to back.
Transmit Data Valid Signal
Each SPORT has its own transmit data valid signal (
is active during the transmission of an enabled word. Because the serial
port's receiver signals are three-stated when the time slot is not active, the
signal specifies if the SPORT data is being driven by the
SPORTx_TDV_0
processor.
After the
TXSPxA
signal is asserted.
SPORTx_TDV
ADSP-214xx SHARC Processor Hardware Reference
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and signal programmed using the SRU. The
SCLK FS
signal initiates the start of the channel 0
SPORTx_FS
period in multichannel is defined as:
FS
× number of channels. The frame sync can be
SLEN
FSED
causes the frame sync to be concurrent with the
MFD
transmit buffer is loaded, transmission begins and the
) is set in the
SPCTLNx
is the number of serial clock
MFD
is 15. A new frame sync
MFD
SPORTx_TDV_0
Serial Ports
IMFS
bit. The edge
LMFS
register.
) which
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