Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 527

The parallel data is acquired through the parallel data acquisition port
(PDAP) which provides a means of moving high bandwidth data to the
core's memory space. The data may be sent to memory as one 32-bit word
per input clock cycle or packed together (for up to four clock cycles worth
of data).
Figure 11-1 provides a graphical overview of the input data port architec-
ture. Notice that each channel is independent and contains a separate
clock and frame sync input.

The IDP provides an easy way to pump serial data into on-chip
memory since it is less complex than the traditional SPORT mod-
ule, limited to unidirectional slave transfers only.
20-BIT
DATA
PDAP
CONTROL
Serial Input Port
IDP_CLK_0
IDP_FS_0
SERIAL TO PARALLEL
32-BIT CONVERSION
IDP_DAT_0
IDP_CLK_x
IDP_FS_x
SERIAL TO PARALLEL
32-BIT CONVERSION
IDP_DAT_x
IDP_CLK_7
IDP_FS_7
SERIAL TO PARALLEL
IDP_DAT_7
32-BIT CONVERSION
Figure 11-1. Input Data Port
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
SIP0
SIPx (x = 6 - 1)
SIP7
CHANNEL 0
CHANNEL x
CHANNEL 7
Input Data Port
IDP
CORE
DMA
INTERNAL
IDP_FIFO
MEMORY
8 x 32-BIT
11-7