Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 187

Self-Refresh Entry
Self-refresh mode causes refresh operations to be performed internally by
the DDR2 controller, without any external control. This means that the
controller does not generate any auto refresh cycles while it is in
self-refresh mode. The self-refresh entry command is performed by writ-
ing a 1 to the
DDR2SRF
deasserts the
DDR2_CKE
mode, the DDR2 on-chip DLL is put into reset in order to reduce power
consumption.
If any of the two DDR2 clocks is not required in a system during
self-refresh, they can be stopped by setting the
control register. This reduces the power consumption in a sys-
DDR2CTL0
tem and is shown in the following code example.
ustat1 = dm(DDR2CTL0);
bit set ustat1 DDR2SRF;
dm(DDR2CTL0) = ustat1;
nop;
ustat2 = dm(DDR2STAT0);
bit tst ustat2 DDR2SRA;
if not TF jump (pc,—2);
ustat1 = dm(DDR2CTL0);
bit set ustat1 DIS_DDR2CTL;
dm(DDR2CTL0) = ustat1;
nop;

This requires careful software control because the
is cleared during runtime. Systems may become unstable if this bit
is cleared too early because the system can lose control of the
DDR2 memory device.
Self-Refresh Exit
The DDR2 remains in self-refresh mode for at least t
internal access to DDR2 space occurs. When exiting from self-refresh
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit of the memory control register (
pin to put the device into self-refresh mode. In this
/* enter self-refresh */
/* test self-refresh entry */
/* freeze DDR2 clock */
External Port
DDR2CTL0
bit in the
DIS_DDR2CTL
DIS_DDR2CTL
and until an
RAS
). This
bit
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