Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 665

• Period value is lower than width value
• Width is equal to period
TIMERx_PERIOD
PCLK
Figure 16-2. Timer Flow Diagram – PWM_OUT Mode
On invalid conditions, the timer sets both the
bits and the Count register is not altered. Note that after reset, the timer
registers are all zero. The PWM_OUT timing is shown in
As mentioned earlier, 2 x
2 x is the width. If the period and width values are valid after the
TMxW
timer is enabled, the count register is loaded with the value resulting from
0xFFFF FFFF – width. The timer counts upward to 0xFFFF FFFF.
Instead of incrementing to 0xFFFF FFFF, the timer then reloads the
counter with the value derived from 0xFFFF FFFF – (period – width) and
repeats.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
CORE BUS
TIMERx_COUNTER
EQUAL?
YES TIMER_ENABLE
1
INTERRUPT
0
PERIOD_CNT
is the period of the PWM waveform and
TMxPRD
Peripheral Timers
TIMERx_WIDTH
RESET
EQUAL?
YES
ASSERT DEASSERT
PWMOUT
PULSE
LOGIC
TIMERx_O
and the
TIMxOVF TIMIRQx
Figure 16-3.
16-9