Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 49

REGISTERS REFERENCE
Overview ..................................................................................... A-2
Register Diagram Conventions ................................................ A-2
Bit Types and Settings ............................................................ A-3
System and Power Management Registers ..................................... A-4
System Control Register (SYSCTL) ......................................... A-4
ADSP-2146x Power Management Registers ............................. A-6
Power Management Control Registers (PMCTL) ................ A-7
Power Management Control Register 1
(PMCTL1) ..................................................................... A-9
ADSP-2147x/ADSP-2148x Power Management Registers ...... A-12
Power Management Control Registers (PMCTL) .............. A-12
Power Management Control Register 1
(PMCTL1) ................................................................... A-15
Running Reset Control Register (RUNRSTCTL) .................. A-18
ADSP-2146x External Port Registers .......................................... A-18
External Port Control Register (EPCTL) ............................... A-18
AMI Control Registers (AMICTLx) ...................................... A-21
AMI Status Register (AMISTAT) .......................................... A-23
DDR2 Registers ................................................................... A-24
DDR2 Control Register 0 (DDR2CTL0) ........................ A-25
DDR2 Timing Control Register 1 (DDR2CTL1) ............ A-29
DDR2 Control Register 2 (DDR2CTL2) ........................ A-31
DDR2 Control Register 3 (DDR2CTL3) ........................ A-33
DDR2 Control Register 4 (DDR2CTL4) ........................ A-35
ADSP-214xx SHARC Processor Hardware Reference
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