Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 963

Table A-78. Group D Sources – Pin Signal Assignments (Cont'd)
Selection Code
1000011 (0x43)
1000100 (0x44)
1000101 (0x45)
1000110 (0x46)
1000111 (0x47)
1001000 (0x48)
1001001 (0x49)
1001010 (0x4A)
1001011 (0x4B)
1001100 (0x4C)
1001101 (0x4D)
1001110 (0x4E)
1001111 (0x4F)
1010000 (0x50)
1011001 (0x51)
1011010 (0x52)
1010011 (0x53)
1010100 – 1111101
1111110 (0x7E)
1111111 (0x7F)
ADSP-214xx SHARC Processor Hardware Reference
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Source Signal
DIR_CLK_O
DIR_TDMCLK_O
DIT_O
SPORT0_TDV_O
SPORT1_TDV_O
SPORT2_TDV_O
SPORT3_TDV_O
SPORT4_TDV_O
SPORT5_TDV_O
SPORT6_TDV_O
SPORT7_TDV_O
DIR_LRCLK_REF_O
DIR_LRCLK_FB_O
PCG_CLKC_O
PCG_CLKD_O
PCG_FSC_O
PCG_FSD_O
Reserved
LOW
HIGH
Registers Reference
Description (Source Selection)
SPDIF_RX Clock Output
SPDIF_RX TDM Clock Output
SPDIF TX Biphase Encoded Data Output
SPORT0 Transmit Data Valid Output
SPORT1 Transmit Data Valid Output
SPORT2 Transmit Data Valid Output
SPORT3 Transmit Data Valid Output
SPORT4 Transmit Data Valid Output
SPORT5 Transmit Data Valid Output
SPORT6 Transmit Data Valid Output
SPORT7 Transmit Data Valid Output
External PLL – Reference Point
Connection
External PLL – Feedback Point Connection
Precision Clock C
Precision Clock D
Precision Frame Sync C
Precision Frame Sync D
Logic Level Low (0)
Logic Level High (1)
A-137