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(
) initiates the transmit operation and reads from this address
UARTTHR
return the
UARTRBR
Note that data is transmitted and received by the least significant bit
(LSB) first (bit 0) followed by the most significant bits (MSBs).
31 30
Zero-Filled
Zero-Filled
Figure 20-3. UART Transmit Holding Register (Packing Enabled)
Receive Buffer Registers (UARTRBR)
The receive operation uses the same data format as the transmit configura-
tion, except that the number of stop bits is always assumed to be 1. After
detection of the start bit, the received word is shifted into the receive shift
register (
UARTRSR
priate number of bits (including stop bit) is received, the data and any
status are updated and the
receive buffer register (
of the received word to the
zation delay, the data ready status flag (
A sampling clock equal to 16 times the baud rate samples the data as close
to the midpoint of the bit as possible. Because the internal sample clock
may not exactly match the asynchronous receive data rate, the sampling
point drifts from the center of each bit. The sampling point is synchro-
nized again with each start bit, so the error accumulates only over the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register.
29 28 27 26 25 24
23 22
15
14
13
12
11 10
9
8
) at a baud rate of
PCLK
UARTRSR
), shown in
UARTRBR
UARTRBR
UART Port Controller
21 20 19 18 17 16
7
6
5
4
3
2
1
/(16 x Divisor). After the appro-
register is transferred to the UART
Figure
20-4. After the transfer
buffer and the appropriate synchroni-
) is updated.
UARTDR
Higher Byte (23–16)
TX9D1
0
Lower Byte (7–0)
TX9D0
20-11
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