Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 226

Data Transfer
LRU VALID
BIT BIT
SET ENTRY 0
0
ENTRY 1
SET ENTRY 0
1
ENTRY 1
SET ENTRY 0
2
ENTRY 1
SET ENTRY 0
13
ENTRY 1
SET ENTRY 0
14
ENTRY 1
SET ENTRY 0
15
ENTRY 1
Figure 3-19. Instruction Cache Architecture
In other words, the 32-entry 2-way set-associative cache in the SHARC
has been modified to act as an instruction cache when the program
sequencer executes instructions from external memory, while continuing
to work as the traditional conflict cache when the sequencer executes
instructions located in internal memory. This context switching from con-
flict cache to instruction cache and vice-versa happens automatically
without the need for any user intervention.
The first time that an instruction from a particular address is fetched from
external memory, there is a cache miss when the sequencer looks for this
instruction within the cache. Consequently, the instruction has to be
fetched from external memory and a copy of instruction is stored in cache.
Upon subsequent executions of this instruction, the sequencer search
results in a cache hit, resulting in the instruction being fetched from cache
instead of external memory. This allows for an instruction throughput
that is equivalent to internal memory execution.
3-96
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INSTRUCTIONS
ADSP-214xx SHARC Processor Hardware Reference
ADDRESSES ADDRESSES
BITS (23-4) BITS (3-0)
0000
0001
0010
1101
1110
1111