Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 866

ADSP-2146x External Port Registers
Table A-19. DDR2STAT1 Register Bit Descriptions (RO) (Cont'd)
Bit Field
23–16
31–24
DLL0 Control Register 1 (DLL0CTL1)
The register shown in
DLL0CTL1
includes the programmable parameters associated with the DLL0 device.
Note that it takes at least 9 core clock cycles to perform a DLL reset.
RESETCAL
Reset the DQS Phase Cali-
bration Logic
Figure A-16. DLL0CTL1 Register
A-40
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Field Name Description
External Bank 2 External Bank 0 Active/Precharge State.
Status xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
...
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
External Bank 3 External Bank 0 Active/Precharge State.
Status xxxxxxx1 = Internal bank 0 in open state
xxxxxxx0 = Internal bank 0 in precharge state
xxxxxx1x = Internal bank 1 in open state
xxxxxx0x = Internal bank 1 in precharge state
...
1xxxxxxx = Internal bank 7 in open state
0xxxxxxx = Internal bank 7 in precharge state
Figure A-16
31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
ADSP-214xx SHARC Processor Hardware Reference
and described in
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
Table A-20
RESETDLL
Reset DLL Control Logic
RESETDAT
Reset Data Capture Logic