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Processor Booting
SPI Port Booting
The SHARC processors support booting from a host processor using SPI
slave mode or booting from an SPI flash, SPI PROM, or a host processor
via SPI master mode. Both SPI boot modes (master and slave) support 8-,
16-, or 32-bit SPI devices. For bit settings, see the product specific proces-
sor data sheet.
In both (master and slave) boot modes, the LSBF format is used
and SPI mode 3 is selected (clock polarity and clock phase = 1).
Both SPI boot modes use default routing with the DPI pin buffers
For more information, see "DPI Default Routing" on page 9-31.
Master Boot Mode
In master boot mode, the processor initiates the booting operation by:
1. Activating the
the active low state.
2. Writing the read command 0x03 and address 0x00 to the slave
device as shown in
Master boot mode is used when the processor is booting from an
SPI-compatible serial PROM, serial FLASH, or slave host processor. The
specifics of booting from these devices are discussed individually.
SPI master booting uses the default bit settings shown in
Table 23-6. SPIDMAC Master/Slave Boot Settings (0x7)
Bit
Setting
SPIDEN
Set (= 1)
SPIRCV
Set (= 1)
INTEN
Set (= 1)
SPICHEN
Cleared (= 0)
23-12
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signal and asserting the
SPICLK
Figure
23-5.
Comment
SPI DMA
SPI receive
SPI interrupt
SPI DMA chaining
ADSP-214xx SHARC Processor Hardware Reference
signal to
SPI_FLG0_O
Table
23-7.
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