Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 706

Features
Table 19-1. Watchdog Timer Specifications (Cont'd)
Feature
DMA Channels
DMA Chaining
Interrupt Source
Boot Capable
Local Memory
Clock Operation
Features
The following list provides a brief description of the watchdog timer's
features.
• Programmable time out period – with about 1 second with 12
MHz clock.
• Time out resets the DSP and asserts the external reset (
pin). DSP is reset internally to the chip upon WDT time out.
• WDT has its own clock (
SHARC
• An internal oscillator to provide the clock input. This internal
oscillator provides a 2 MHz (typical frequency) clock.
• Status bit available for the processor to read which is cleared on
hardware reset assertion – it is not cleared on WDT generated
reset.
19-2
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WDT_CLKIN
and any other clock derived from
CLKIN
ADSP-214xx SHARC Processor Hardware Reference
Availability
N/A
N/A
N/A
N/A
N/A
WDTCLKIN
) that is independent from the
WDTRSTO
.
CLKIN