Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 363

Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
IIR Accelerator Effect Latency
After the IIR registers are configured the effect latency is 1.5
minimum and 2
an effect latency of two
selecting another accelerator before accessing any of its registers.
IIR Throughput
Data throughput is one 32-bit data word per peripheral clock cycle for
writes to memory, provided there are no conflicts. Read throughput from
memory, throughput is one 32-bit data word per two peripheral clock
cycles.
IIR throughput is calculated as follows:
Total number of peripheral clock cycles = (TCB load + 5 × B × W) × C
where:
• B = number of bi-quads
• W = Window size
• C = number of channels
• TCB load = 36
• 5 × B – Number of cycles to calculate B biquads (Note: This does
not include the coefficient loading cycles as coefficients need to be
loaded only once.)
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
cycles maximum. Writes to the
PCLK
cycles. Wait for at least four
PCLK
cycles
PCLK
FFT/FIR/IIR Hardware Modules
PMCTL1
cycles
PCLK
register have
cycles after
CCLK
6-67