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IIR Accelerator
Programming Model
The IIR supports up to 24 channels which are time division multiplexed
(TDM). Each channel can have a maximum of 12 cascaded biquads. The
window size for each channel is configurable using control registers. A
window size of 1 corresponds to sample based operation and the maxi-
mum window size is 64.
The coefficients are initially stored in internal memory and one TCB per
channel is created in internal memory with each channels' TCB pointing
to the next channels'. The TCB also contains channel specific control reg-
isters, input data buffer parameters and output data buffer parameters.
The TCB of the last channel should point to the TCB of first
channel.
The total number of channels is configured using the
DMA is enabled.
The procedure that the accelerator uses to process biquads is shown in
Figure 6-14
and described in the following procedure.
1. The controller loads all coefficients of all the channels into local
storage.
2. Once all the coefficients are loaded, the controller goes to the first
biquad of the first channel and calculates the output of the first
biquad and updates the intermediate results for that biquad.
3. Then, the accelerator moves to the next biquad of that channel and
repeats the process until all the biquads for that channel are com-
pleted and the results are stored to memory.
4. This process is repeated with next sample until one window of the
corresponding channel is processed.
5. After one window of the channel accelerator is processed, the accel-
erator moves to the next channel and computes the results.
6-68
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ADSP-214xx SHARC Processor Hardware Reference
register and
IIRCTL1
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