Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 870

ADSP-2146x External Port Registers
DDR2 Pad Control Register 1 (DDR2PADCTL1)
The
DDR2PADCTL1
Table A-24 includes the programmable parameters associated with the
DDR2 Command (
31 30
15
ADDR_PWD
Receiver Power Down
Figure A-19. DDR2PADCTL1 Register
Table A-24. DDR2PADCTL1 Register Bit Descriptions (RW)
Bit Name
8–0 Reserved
9 ADDR_PWD
18–10 Reserved
19 CMD_PWD
28–31 Reserved
A-44
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register shown in
, , ,
CS CAS RAS WE
29 28 27 26 25 24
14 13 12 11 10 9 8 7
Description
Address Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
Command Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
ADSP-214xx SHARC Processor Hardware Reference
Figure A-19 and described in
, ) and Address pad control.
ODT
23 22 21 20 19 18 17 16
6 5 4 3 2 1 0
CMD_PWD
Receiver Power Down