Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 971

DAI Shift Register Routing Registers
(Group G, ADSP-2147x)
The pin enable control registers (see
Table A-81, Table
pins. When the pins are not enabled (driven), they can be used as inputs.
Clock Routing Register (SRU_CLK_SHREG)
The shift register's
either logic 0 , logic 1, the SPORT0–7 clock and frame sync signals, the
PCG A and PCG B clock and frame sync signals,
DAI pin buffers 1–8.
and programmable options for
15 14 13
SR_LAT_I (9–5)
Latch Input
Figure A-81. SR_CLK_SHREG Register (RW)
Table A-81. Group G Sources – Shift Register Clock Routing
Selection Code
00000 (0x0)
00001 (0x1)
00010 (0x2)
00011 (0x3)
00100 (0x4)
00101 (0x5)
00110 (0x6)
00111 (0x7)
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
A-82) activate the drive buffer for each of the 20 DAI
and
SR_SCLK_I
Figure A-81
SR_SCLK_I
12 11 10 9 8 7 6
Source Signal
LOW
HIGH
SPORT0_CLK_O
SPORT1_CLK_O
SPORT2_CLK_O
SPORT3_CLK_O
SPORT4_CLK_O
SPORT5_CLK_O
Registers Reference
Figure A-81, Figure
input signals can come from
SR_LAT_I
SR_SCLK_I
and Table A-81 show the list of sources
and
SR_LAT_I
5 4 3 2 1 0
SR_SCLK_I (4–0)
Serial Clock Input
Description (Output Source Selection)
Logic Level Low (0)
Logic Level High (1)
Sport 0 Clock Output
Sport 1 Clock Output
Sport 2 Clock Output
Sport 3 Clock Output
Sport 4 Clock Output
Sport 5 Clock Output
A-82, and
, , or
SR_LAT
input signals.
A-145