Dead Time - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Functional Description
T AH
d ----------- -
= =
AH
T
H
since for the general case in double- update mode, the switching period is
given by:
T
S
Again, the values of T
T . Similar PWM signals to those illustrated in
S
can be produced on the BH and BL outputs by programming the
registers in a manner identical to that described for the

Dead Time

The second important parameter that must be set up in the initial config-
uration of the PWM block is the switching dead time. This is a short delay
time introduced between turning off one PWM signal (say
ing on the complementary signal,
to permit the power switch being turned off (
recover its blocking capability before the complementary switch is turned
on. This time delay prevents a potentially destructive short-circuit condi-
tion from developing across the DC link capacitor of a typical voltage
source inverter.
The 10-bit, read/write
time, T , is related to the value in the
d
Therefore, a PWMDT value of 0x00A (= 10), introduces a 200 ns delay
between when the PWM signal (for example
plementary signal (
7-12
www.BDTIC.com/ADI
(
PWMCHA 1 PWMCHA 2 PWMDT 1 PWMDT 2
+
1
-- - ----------------------------------------------------------------------------------------------------------------------------------------- -
+
(
2 PWMPERIOD
(
PWMPERIOD
= +
1
and T
AH AL
AL
registers control the dead time. The dead
PWMDT3–0
T = PWMDT
d
) is turned on. The amount of the dead time can
AL
ADSP-214xx SHARC Processor Hardware Reference
–
PWMPERIOD
+
1
) ×
PWMPERIOD t
2 PCLK
are constrained to lie between zero and
Figure 7-2
. This short time delay is introduced
in this case) to completely
AH
registers by:
PWMDTx
× ×
t
2
PCLK
) is turned off and its com-
AH
)
–
)
2
and Figure 7-3
PWMBx
registers.
PWMAx
) and turn-
AH