Sdram Read Optimization - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

SDRAM Controller (ADSP-2147x/ADSP-2148x)
ADDR [15]
RAS
C
O
CAS
N
SDWE
T
R
SDCKE
O
MS3
L
A[12-11]
A
D
A[9-0]
D
SDA10
R
E
A17
S
A18
S
SDCLK
DATA [15-0]
SDDQM
Figure 3-10. Uniprocessor System With Multiple Buffered SDRAM
Devices

SDRAM Read Optimization

To achieve better performance, read addresses can be provided in a predic-
tive manner to the SDRAM memory. This is done by setting (=1) the
bit (bit 16) and correctly configuring the
SDROPT
3-40
www.BDTIC.com/ADI
21
D Q
CTRL [6]
SDRAM BANK 1
ADDR & CTRL
21
D Q
SDRAM BANK 2
ADDR & CTRL
REGISTERED
BUFFERS
O0A
I0
O1A
I1
O2A
I2
O3A
I4
O4A
I5
OXA[12-0]
IXA[12-0]
ADSP-214xx SHARC Processor Hardware Reference
SDRAM #1
32M x 4 x 4
RAS
DQM
CAS
WE
CKE
CS
A[14-0]
CLK
DATA [3-0]
DATA [3-0]
DATA [7-4]
DATA[3:0]
SDRAM #2
32M x 4 x 4
DATA [11-8]
DATA[3:0]
DATA [15-12]
bits
SDMODIFY
DQM
DQM
DQM
SDRAM #3
32M x 4 x 4
DATA[3:0]
SDRAM #4
32M x 4 x 4