Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 647

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Core Master Transfers

When a device is to be used as a master, configure the ports using the fol-

lowing procedure.

1. Initiate the SPI transfer by writing or reading to/from SPI buffers.

The trigger mechanism for starting the transfer is dependant upon

2. The SPI generates the programmed clock pulses on

data is shifted out of

Before starting to shift, the transmit shift register is loaded with the

contents of the

tents of the receive shift register are loaded into the

3. With each new buffer access, the SPI continues to send and receive

words, according to the SPI transfer mode (

registers). See

4. If there are no further SPI buffer accesses the

stalled until new core requests are received.

DMA Master Transfers

To configure the SPI port for master mode DMA transfers:

1. Define DMA receive (or transmit) transfer parameters by writing

2. Write to the

, bit 0). And configure the following:

• A receive access (

• A transmit access (

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

Serial Peripheral Interface Ports

for more details.

and shifted in from

registers. At the end of the transfer, the con-

Table 15-6 on page 15-13

registers. See

Table 15-6 on

for more details.

simultaneously.

bit in SPICTLx

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