Logic Level Frame Syncs; Data-Independent Frame Sync - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Functional Description

Logic Level Frame Syncs

Frame sync signals may be active high or active low (for example,
inverted). The
LFS
the frame sync signals as active low (inverted) if set (=1) or active high if
cleared (=0). Active high (=0) is the default.

Data-Independent Frame Sync

When = 0 and
DIFS
sync is only output when a new data word has been loaded into the
SPORT channel's transmit buffer. Once data is loaded into the transmit
buffer, it is not transmitted until the next frame sync is generated. This
mode of operation allows data to be transmitted only at specific times.
When = 0 and
DIFS
only when receive data buffer status is not full.
The data-independent frame sync mode allows the continuous generation
of the
SPORTx_FS
bit of the
SPCTLx
and = 1, a transmit
SPTRAN
transmit data buffer status. When
signal is generated regardless of the receive data buffer status.
SPORTx_FS
Note that the SPORT DMA controller typically keeps the transmit buffer
full. The application is responsible for filling the transmit buffers with
data.
10-20
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/ bit in the
LMFS SPCTLx
= 1, the internally-generated transmit frame
SPTRAN
= 0, a receive
SPTRAN
signal, with or without new data in the buffers. The
control register configures this option. When
SPORTx_FS
DIFS
ADSP-214xx SHARC Processor Hardware Reference
registers selects the logic level of
signal is generated
SPORTx_FS
signal is generated regardless of the
= 1 and = 0, a receive
SPTRAN
DIFS
= 1
DIFS