Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 565

between two or more adjacent sample rate converters that are operating
with the same input and output clocks. When the
(=1), the SRC, a matched phase mode slave accepts the sample rate ratio
transmitted by another SRC, the matched phase mode master, through its
serial output as shown in
DATA INPUT 2
SRC2_DAT_IP_I
SRC2_TDM_IP_O
MASTER
SPORT_Dx_I
FSout, CLKout = 32 x FSout
Figure 12-5. Typical Configuration for Matched-Phase Mode Operation
The phase master SRC device transmits its
through the data output pin (
input pins (
SRCx_TDM_OP_I
tains 24-bit data and 8-bits matched phase. The slave SRCs receive the
8-bit matched phase bits (instead of their own internally-derived ratio) if
their
SRCx_MPHASE
The
SRCx_FS_IP
respect to each other in this mode. Note there must be 32
ADSP-214xx SHARC Processor Hardware Reference
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Asynchronous Sample Rate Converter
Figure 12-5.
DATA INPUT 1
SRC1_DAT_IP_I
SRC1_TDM_IP_O
SRC2_TDM_OP_I
PHASE
SLAVE
SRC2_DAT_OP_O
DATA OUTPUT 1
SRCx_DAT_OP_O
). The transmitted data (32-bit subframe) con-
bits set to 1, respectively.
and signals may be asynchronous with
SRCx_FS_OP
SRCx_MPHASE
CLKin, FSin
SRC0_DAT_IP_I
SRC0_TDM_IP_O
SRC1_TDM_OP_I
PHASE
SLAVE
SRC1_DAT_OP_O
DATA OUTPUT 0
/
SRCx_FS_OP SRCx_FS_IP
) to the slave's SRC's data
bit is set
Non-TDM IP
SPORT_Dx_O
MASTER
SRC0_TDM_OP_I
PHASE
MASTER
SRC0_DAT_OP_O
Non-TDM OP
ratio
SRCx_CLK_OP
12-13