Sdram Controller; Power-Up Sequence - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Programming Models

SDRAM Controller

This section describes software programming steps required for the suc-
cessful operation of the SDC.

Power-Up Sequence

After reset, the
the SDC must be configured and initialized. In order to set up the SDC
and start the SDRAM power-up sequence for the SDRAMs, use the fol-
lowing procedure. Note that the registers must be programmed in order.
1. Chose a valid
2. Wait at least 15 core clock cycles until the new
been settled up correctly.
3. Assign external banks to SDC in the
4. Wait at least 8 core clock cycles (effect latency).
5. Program the refresh counter in the
6. Define global control for SDC and SDRAM based on speed and
SDRAM specifications in the
7. Once the
is required to start the power-up sequence.
The SDRAM is ready for access.
The bit (bit 3) of the SDRAM control status register can be checked
SDRS
to determine the current state of the SDC. If this bit is set, the SDRAM
power-up sequence has not been initiated.
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is running with the default PLL settings. However,
SDCLK
to
CCLK SDCLK
bit in the
SDPSS SDCTL
ADSP-214xx SHARC Processor Hardware Reference
clock ratio in the
PMCTL
SDCLK
register.
EPCTL
register.
SDRRC
register.
SDCTL
register is set to 1, a dummy access
register.
frequency has