Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 745

CORE BUS
TWI
INTERFACE
IRQ
Figure 21-1. TWI Block Diagram
The address compare block supports address comparison in the event the
TWI controller module is accessed as a slave.
The prescaler block must be programmed to generate a 10 MHz time ref-
erence relative to the peripheral clock. This time base is used for filtering
data and timing events specified by the electrical parameters in the data
2
sheet (see the I
clock generation.
The clock generation module is used to generate an external serial clock
( ) when in master mode. It includes the logic necessary for syn-
TWI_CLOCK
chronization in a multimaster clock configuration and clock stretching
when configured in slave mode.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
FIFO
REGISTERS
C bus specification from Philips), as well as for
Two Wire Interface Controller
TWI_DATA_PBEN_O
TRANSMIT SHIFT
REGISTER
ARBITRATION
RECEIVE SHIFT
REGISTER
ADDRESS COMPARE
PRESCALER
TWI_CLK_PBEN_O
CLOCK GENERATION
(OPEN DRAIN)
TWI_DATA_I
(OPEN DRAIN)
PCLK
TWI_CLK_I
TWI_CLOCK
21-7