Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 940

Peripheral Registers
Watchdog Timer Registers
The following sections provide bit descriptions for the registers associated
with the watchdog timer.
Control (WDTCTL)
The watchdog control register (
ory-mapped register used to configure the watchdog timer.
protected against accidental writes from the processor core by the watch-
dog unlock register (
without an unlock command causes the WDT to expire, and reset the sys-
tem. This condition is captured in the watchdog exception field (
Writes made by software to this register keep it enabled. Only an External
hardware reset can disable
Status (WDTSTATUS)
The
WDTSTATUS
Table A-72, contains the watchdog timer status information. This register
is not cleared by the WDT generated reset.
15 14
WDERR
Error
Figure A-51. WDTSTATUS Register
A-114
www.BDTIC.com/ADI
WDTCTL
). Attempts by the core to write to
WDTUNLOCK
.
WDTCTL
register, shown in Figure A-51
13 12 11 10 9 8 7 6
ADSP-214xx SHARC Processor Hardware Reference
), is a 32-bit system mem-
and described in
5 4 3 2 1 0
WDRO
Slave Transfer Direction
is
WDTCTL
WDTCTL
).
WDERR