Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 781

bit set ustat2 PLLBP | PLLD4 |PLLM16;
dm(PMCTL) = ustat2;
waiting_loop:
r0 = 4096;
lcntr = r0, do pllwait until lce;
pllwait: nop;
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP;
dm(PMCTL) = ustat2;
bit set ustat2 DIVEN;
dm(PMCTL) = ustat2;
lcntr = 15, do pllwait1 until lce;
pllwait1: nop;
Back to Back Bypass
Use this steps and the example shown in
needs to re-enter the bypass mode.
1. Disable the bypass bit in the
2. Wait 6 core clock cycles.
3. Enable the bypass bit.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
/* set a multiplier of
16 and a divider of 4 */
/* wait for PLL to lock at new rate
(requirement for VCO change) */
/* Reading the PMCTL register value
returns the DIVEN bit value as zero.
The DIVEN bit should be cleared while
taking the PLL out of bypass mode
/* take PLL out of Bypass,
PLL is now at new CCLK) */
/* Enable the divider */
Listing 22-5
register.
PMCTL
Power Management
if the application
*/
22-17