Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 862

ADSP-2146x External Port Registers

This register's contents should not be changed while the DDR2
interface is active. Also, whenever this register's contents are
changed an initialization sequence must be executed to reflect this
register's contents in the
Table A-16. DDR2CTL5 Register Bit Descriptions (RW)
Bit
13–0
15–14
Refresh Rate Control Register (DDR2RRC)
The DDR2 refresh rate control register
provides a flexible mechanism for specifying the auto-refresh timing. The
delay (in number of
counter time-outs must be written to the
tion, see "Refresh Rate" on page 3-33.
31 30
15 14
Figure A-13. DDR2RRC Register
A-36
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DDR2EMR2
Name Description
Reserved.
DDR2EXTMR3 Extended Mode Register 3.
Must be set to 11.
cycles) desired between consecutive refresh
DDR2CLK
29 28 27 26 25 24 23 22
13 12 11 10 9 8 7 6
ADSP-214xx SHARC Processor Hardware Reference
register.
(Figure A-13 and
field. For more informa-
RDIV
21 20 19 18 17 16
tRFC (28–21)
Refresh Interval
5 4 3 2 1 0
Table A-17)
RDIV (13–0)
Refresh Count