Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 856

ADSP-2146x External Port Registers
Table A-12. DDR2CTL1 Register Bit Descriptions (RW)
Bit
4–0
8–5
11–9
15–12
18–16
21–19
A-30
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Name Description
DDR2TRAS Row Active Time.
00000 = Reserved
00001 = 1 clock cycle
00010 = 2 clock cycles
...
11111 = 31 clock cycles
DDR2TRP Row Precharge Time. Note that for 8 banked devices the
timing spec becomes t
0000 = Reserved
0001 = 1 clock cycle
0010 = 2 clock cycles
...
1111 = 15 clock cycles
DDR2TWTR Write to Read Delay.
000 = Reserved
001 = 1 clock cycle
010 = 2 clock cycles
...
111 = 7 clock cycles
DDR2TRCD RAS to CAS Delay.
000 = Reserved
001 = 1 clock cycle
010 = 2 clock cycles
...
111 = 7 clock cycles
Reserved
DDR2TRTP Read to Precharge Delay.
000 = Reserved
001 = 1 clock cycle
010 = 2 clock cycles
...
111 = 7 clock cycles
ADSP-214xx SHARC Processor Hardware Reference
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