Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 719


The 16-bit divisor formed by the
resets to 0x0001, resulting in the highest possible clock frequency
by default. If the UART is not used, disabling the UART clock
saves power (see bits 13 and 14 in the
ment Registers" on page
can be programmed by software before or after turning on the
clock.
Table 20-3 provides example divide factors required to support most stan-
dard baud rates.
Table 20-3. UART Baud Rate Examples With 100 MHz PCLK
Baud Rate
2400
4800
9600
19200
38400
57600
115200
921,600
6,250,000

Careful selection of
desired baud rates, can result in lower error percentages.
Functional Description
The UART supports multiprocessor communication using 9-bit address
detection. This allows the units to be used in multi-drop networks using
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
A-4). The
Divisor Latch Actual
(DL)
2604 2400.15
1302 4800.31
651 9600.61
326 19,171.78
163 38,343.56
109 57,339.45
54 115,740.74
7 892,857.14
1 6,250,000
frequencies, that is, even multiples of
PCLK
UART Port Controller
and
UARTDLH UARTDLL
"System and Power Manage-
and
UARTDLH UARTDLL
% Error
0.006
0.007
0.006
0.147
0.147
0.452
0.469
3.119
–
registers
registers
20-5