Ddr2 - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table of Contents

The first access does the explicit 32-bit access (which results in the physi-

cal space in 2x16-bit words) while the 2nd 32-bit access does the implicit

transfer. In total there are four read or write commands as shown in

Table 3-16. SDRAM SIMD Access

DDR2

For a SIMD transfer, the controller can burst the 64-bit data given by the

core and writes it to N and N+1 memory locations. Since the burst length

is 4, SIMD mode transfers can be performed within one burst access.

The first access does the explicit 32-bit access (which results in the physi-

cal space in 2x16-bit words) while the 2nd 32-bit access dperforms the

implicit transfer. In total there is one read or write command per burst of

4x16-bit data as shown in

Table 3-17. DDR2 SIMD Burst Access

DM(0x200000) = R0

DM(0x200001) = S0

ADSP-214xx SHARC Processor Hardware Reference

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DM(0x200000) = R0

DM(0x200001) = S0

Physical x16

DM(0x400000) = R0(LSW);

DM(0x400001) = R0(MSW);

DM(0x400002) = S0(LSW);

DM(0x400003) = S0(MSW);