Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 599

PCG C and D cannot be directly connected to other peripheral
clock and frame sync signals. They can only be routed through the
DAI pins.
Register Overview
The processor contains registers that are used to control the PCGs.
• Control Register 0 (PCG_CTLx0). Enables the clock and frame
sync, it includes the frame sync divider and the upper half of the
20-bit phase value.
• Control Register 1 (PCG_CTLx1). Enables the clock and frame
sources, it includes the clock divider and the lower half of the
20-bit phase value.
• Pulse Width Register (PCG_PWx). Contains the pulse with set-
tings for normal mode (
( = 1/0). Enables direct bypass or one shot mode.
FSDIV
• Synchronization Register (PCG_SYNCx). This register enables
as input clock to the PCGs. It also enables external FS trigger
PCLK
mode.
Clocking
The fundamental clock of the PCG is
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Precision Clock Generator
> 1) or control bits for bypass mode
FSDIV
.
PCLK
14-5