Core Accesses - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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(bits 20–17) in the

the DMA's modify parameter register.

The predictive address given to the memory depends on the

values. For example, if the DAG modifier = 2, the

also be 2, in which case the address + 2 is the predictive value provided to

the SDRAM address pins. Programs may choose to determine whether

read optimization is used or not. If read optimization is disabled, then

each read takes 7 cycles for a CAS latency of 3, even for sequential reads.

With read optimization enabled, 32 sequential reads, with offsets ranging

from 0 to 15, take only 37

enabled while reading at the external bank boundaries. For example, if

= 1, then 32 locations in the boundary of the external banks

should not be used. These locations can be used without optimization

aries of the external bank (if it is fully populated).

It is advisable to use read optimization for core and DMA, with a constant

modifier to achieve better performance. With multiple channels running

with ping-pong accesses, use arbitration freezing to get better throughput.

By default, the read optimization is enabled (

modifier of 1 (

SDRAM pointer has a constant modifier. For non-sequential

accesses, turning off optimization provides better results.

Core Accesses

Any break of sequential reads of full page accesses can cause a throughput

loss due to a maximum of four extra reads (eight 16-bit reads).

shows how to achieve maximum throughput using core accesses. Any cycle

between consecutive reads to an SDRAM address results in non-sequential

ADSP-214xx SHARC Processor Hardware Reference

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cycles. Read optimization should not be

= 2, then 64 locations cannot be used at the bound-

= 1). Read optimization assumes that the

External Port

value should

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