Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 342

FIR Accelerator
Bit 11 of the
DBGADDR
selects delay line memory in cleared (=0).
In the debug mode, the read data register (
tents of the memory location pointed to by the address register. Data can
be written into any memory location using
the address auto increment bit (
auto increments on
auto increment, the
coefficient memory boundary.
Single Step Mode
Programs can single step through the MAC operations and observe the
memory contents after each step. The
bits control the FIR MAC units.
Emulation Considerations
In FIR debug mode, the DMA operations are not observable.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
FIR Accelerator Effect Latency
After the FIR registers are configured the effect latency is 1.5
minimum and 2
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register selects coefficient memory if set (=1) and
FIR_ADRINC
writes and
DBGMEMWRDAT
register cannot cross the data memory/
FIR_DBGADDR
cycles maximum. Writes to the
PCLK
ADSP-214xx SHARC Processor Hardware Reference
) returns the con-
DBGMEMRDDAT
register writes. If
DBGMEMWRDAT
) is set, the address register
DBGMEMRDDAT
/
FIR_DBGMODE FIR_HLD
PMCTL1
reads. During
and
FIR_RUN
cycles
PCLK
register have