Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 871

ADSP-2147x, ADSP-2148x External Port
Registers
The registers in the following sections are specific to the ADSP-2147x and
the ADSP-2148x external port and include the external port, the SDRAM
controller, and AMI registers.
External Port Control Register (EPCTL)
The external port control register can be programmed to arbitrate the
accesses between the processor core and DMA, and between different
DMA channels. These registers are shown in
Table A-25.
DATEN (15–18)
FRZCR (14–12)
Arbitration Freezing Length for
CORE Accesses
FRZDMA (10–8)
Arbitration Freezing Length for DMA
DMAPR (7–6)
DMA Channel Priority for CH0 and CH1
Figure A-20. EPCTL Register
ADSP-214xx SHARC Processor Hardware Reference
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31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
Registers Reference
Figure A-20
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
and described in
DATEN (15–18)
EP Data Mask Enable
B0SD
Bank 0 SDRAM
B1SD
Bank 1 SDRAM
B2SD
Bank 2 SDRAM
B3SD
Bank 3 SDRAM
EPBR (5–4)
External Port Bus Priority
A-45