Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 772

Power-Up Sequence
Normal Mode
The normal mode is the regular mode and is effective if the
cleared. In normal mode the PLL has locked and multiplies
desired VCO clock. The output clock generator post divides and provides
the clock tree to the I/O.

The change of PLL frequency can happen at any time (for example
after power-up or during operation).
Clocking Golden Rules
The five rules below should be followed to ensure proper processor
operation.
1. After power-up the
core speed.
2. Software should guarantee minimum/maximum
3. Software should guarantee maximum VCO clock speed.
4. Bypass requires 4096
5. Post divider changes require 14
Power-Up Sequence
The proper power-up sequence is critical to correct processor operation as
described in the following sections.
22-8
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pins should not exceed the maximum
CLK_CFG
cycles.
CLKIN
CCLK
ADSP-214xx SHARC Processor Hardware Reference
PLLBP
CLKIN
speed.
CCLK
cycles.
bit is
to the