Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 938

Peripheral Registers
The 5-bit offset of the DMA address comes from the base address
registers.
Table A-69. MLB_CCBCRx Register Bit Descriptions (RO)
Bit
1–0
15–2
17–16
31–18
Channel x Next Buffer Configuration Registers (MLB_CNBCRx)
These registers, described in
start and end address of the next buffer in internal memory for the logical
channel in DMA mode. When configured in I/O mode, these registers
implement the transmit data buffer. The definition of bit fields in this reg-
ister vary dependant on the selected channel type and are read-write.
Table A-70. MLB_CNBCRx Register Description (RW)
Bit
1–0
15–2
17–16
31–18
Local Buffer Configuration Registers (MLB_LCBCRx)
These registers, described in
use of the local channel buffer memory. These registers should only be
written by software while the logical channel is disabled. The size of the
local channel buffer RAM is 124 words. At reset, this RAM is shared
A-112
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Name Description
Reserved for other channel types
BFA Buffer Final Address.
Reserved for other channel types
BCA Buffer Current Address.
Table
Name Description
Reserved for other channel types
BEA Next Buffer End Address.
Reserved
BSA Next Buffer Start Address.
Table
ADSP-214xx SHARC Processor Hardware Reference
A-70, allows system software to set the
A-71, allow software to optimize the